In recent years, it has been found that, along with a progression of miniaturization of transistors, electrical characteristics of transistors largely vary depending on stresses on the transistors.
Therefore, in evaluating the characteristics of transistors, while it is necessary to prepare transistors having various layouts to measure a gate length, a gate width, a source/drain width, a device area space, well proximity, and the like, the arrangeable number of transistors is largely restricted at present due to restrictions on an area where the transistors are to be arranged.
As a technology for improving such a situation, there is a transistor array TEG (Test Element Group) in which transistors are arranged in an array and switches of the transistors to be measured are switched by a switch circuit (see Patent Document 1). A mainstream configuration of such a transistor array TEG is that a switch such as a CMOS switch is interposed between each of a gate/source/drain and a pad, and on/off of the switches is controlled by a selector circuit.
Patent Document 1: Japanese Patent Application Laid-open No. 2008-288902